In the fabrication of semiconductor memory chips, there are typically some memory elements in the chip that post-fabrication testing shows to be defective. Because such defective memory elements do occur with some regularity in chip fabrication, and because memory chips of the current art are commonly fabricated to contain several megabytes of memory, it is not economically feasible to reject all chips found to include any defective memory elements. Moreover, in the usual case, the number of the defective memory elements found is small compared with the total number of memory elements in the chip memory array. Thus, on-chip repair techniques have been developed to enable repair of chips having relatively small numbers of defects, and accordingly to improve production yield.
Although a variety of on-chip repair techniques are known in the art, all rely, at least in principle, on the idea of replacing defective memory elements in a chip with extra or spare memory elements included in the chip, over and above those required for the chip memory array. In the usual case, a memory chip or embedded memory module is made up of an array of memory elements identified by rows and columns (each row/column intersection defining a memory element). The array may also be subdivided into multiple blocks. A block is a relatively small array of intersecting rows and columns residing within the main memory array. Extra rows, columns and/or blocks are added to the chip to accommodate the replacement of bad elements. While replacement could be made at the level of individual memory elements, considerations of practicality generally dictate that an entire row, column, or block containing one or more defective memory elements be replaced.
To perform the replacement of defective memory elements, the defective rows, columns, blocks or cells of a chip are first identified, usually during wafer probe testing of a plurality of such chips fabricated together in a form known in the art as a wafer. Testing may be effected by an external test set or by embedded Built-In-Self-Test (BIST) circuitry. Once the defective elements are identified, one of two general methods for repair of those defective elements is commonly used.
In one process, denoted hard repair, upon a defective row, column or block of memory elements being identified, a replacement row, column or block is permanently substituted for the defective elements, typically by laser repair. A defining characteristic of all hard repair techniques is that of the replacement elements being permanently substituted for the defective elements.
In a somewhat newer process, denoted soft repair, no permanent replacement of defective memory elements is made. Rather, the memory chip is tested and reconfigured—i.e., by replacement of defective elements with good rows, columns and/or blocks—each time the chip is powered up.
A problem arises, however, with soft repair, in that the techniques of the art do not deal well with the circumstance of variations in defective elements, and their identification, occurring with changes in the operating environment for the chip.
Specifically, the presence and location of defective semiconductor memory elements may change with changes in chip operating environment, e.g. voltage and/or temperature. Soft repair will occur under one set of environmental conditions, but during subsequent operation of the chip, environmental conditions may change—i.e., temperature may rise or fall and voltage may vary, both within some specified range. The changing environmental conditions may uncover additional defective elements. Chips experiencing additional defects during such changing environmental conditions need to be labeled as “defective” and discarded. Only chips that do not experience additional defective elements with variations in environmental conditions (within the specified range), should be labeled as “good” and made available.